Verilog TCL Quiz

What is the default value for reg data type

• 0

• 1

• x

• d

In continuous assignment left hand side must be

• Net

• Reg

• Scalar or Vector Net 

• Scalar or Vector Net 

If x=4 b1100 then x<<2 is

• 4 b1000

• 4 b0000

• 4 b0011

• 4 b0110

#40 $finish indicates

• end of simulation time

• end of simulation after 40 time units 

• suspend simulation at 40 time units

• delay for 40 time units and then execute next line after $finish

What do you mean by logic synthesis?

• RTL description is converted in terms of logic gates by the use of synthesis tool

• RTL description is simulated and the simulation waveforms are shown by synthesis tools

• RTL description is remodelled from behavioural to data flow modelling by synthesis tools

• RTL description is checked for any errors by synthesis tools

what is the correct set of Verilog code to swap contents of two register with and without temporary registers.

• 
• 
• 
• 

What is wrong with following piece of code

• 1. Nothing wrong

• 2. incorrect a and b can overflow as it is incremented in an infinite loop

• 3. Simulation may not advance since forever doesn't have any timing control

• A forever block cannot be used inside an initial block

What is order of execution for below code?

• Zero delay control statement is executed first

• Zero delay is executed only after all other statements

  are executed in that simulation time and order of zero

• delay statement is non deterministic

• Zero delay control statement is executed last

Which is true about task and function

• Task and function contain always and initial blocks

• Task and function do not contain always and initial blocks

• Task and function do not contain behavioral statement

• Task and function can not have global variables called

For the below code segment given below

• Values of a and b are swapped

• Values of a and b cannot be swapped 

• Values of a and b can be swapped depending on simulato

• Can t determine