sudhikssha

What will be the output of the following code? module test; reg [3:0] a = 4'b1010; initial $display("%d", a); endmodule

• 10
• 1010
• 4
• Error

What is the value of out after this always block executes? always @(a or b) begin out = a &b; end

• Bitwise AND of a and b
• Logical AND of a and b
• Sum of a and b
• Bitwise OR of a and b

What does the always block below describe? always @(posedge clk) q <= d;

• Combinational logic
• Asynchronous latch
• D Flip-Flop
• Counter

What will be the output y if a=1 and b=1 in the following? assign y = ~(a & b);

• 1
• 0
• X
• Z

Which of the following data types is NOT supported in Verilog?

• reg
• wire
• int
• bit_vector

Which of the following is used to simulate delay in Verilog?

• @
• #
• $
• %

Which of the following describes a blocking assignment in Verilog?

• <=
• ->
• =
• <<=

In Verilog, what kind of assignment does assign perform?

• Sequential
• Blocking
• Continuous
• Procedural

What is the default value of a reg type in Verilog if not initialized?

• 1
• 0
• X
• Z

Which keyword is used to stop simulation in Verilog?

• Halt
• Exit
• $end
• $finish