Pseudo NMOS Logic Quiz

In a pseudo-NMOS inverter, rise time is primarily affected by:

• PMOS transistor strength

• NMOS transistor strength

• Load capacitance only

• Threshold voltage

Fall time in a pseudo-NMOS inverter is dominated by the:

• PMOS transistor

• Body effect

• NMOS transistor

• Channel length modulation

Which of the following best describes the transient response in pseudo-NMOS logic?

• Symmetric rise and fall times

• Faster rise than fall

• Slower rise than fall

• No transient behavior

Why is the rise time longer in pseudo-NMOS logic compared to CMOS?

• PMOS is stronger than NMOS

• PMOS is always OFF

• PMOS is always ON and weak

• NMOS is slow

What effect does increasing load capacitance have on rise and fall times in pseudo-NMOS logic?

• Increases both rise and fall times

• Decreases both

• Affects only fall time

• No effect

Which of the following best describes the operation of the pseudo-NMOS inverter at logic '0' input?

• Both NMOS and PMOS are OFF

• NMOS is ON, PMOS is OFF

• NMOS is OFF, PMOS is ON

• Both NMOS and PMOS are ON

The threshold point of a pseudo-NMOS inverter shifts towards:

• Ground

• VDD

• Midpoint of VDD

• Zero

Why does the pseudo-NMOS inverter not have rail-to-rail output swing?

• Due to clocked NMOS

• Because PMOS is weak

• Because NMOS is always OFF

• Because PMOS is always ON

What causes static power dissipation in pseudo-NMOS logic?

• Floating nodes

• Gate leakage

• Simultaneous conduction of PMOS and NMOS

• Slow rise time

If the NMOS width is increased (keeping PMOS width constant), what happens to the output high voltage (VOH)?

• It increases

• It decreases

• It remains unchanged

• It becomes undefined