Verilog Basics Quiz

What is the keyword used to define a module in Verilog?

• entity

• module

• design

• model

Which of the following are valid Verilog port directions? (Multiple Choice)

• input

• output

• inout

• signal

What type of port can both receive and send data in Verilog?

• input

• output

• inout

Which keyword is used to end a module in Verilog?

• endmodule

• endmodule;

• end

• finish

A module in Verilog can have multiple instances inside another module.

• True

• False

Which keyword is used for continuous assignment in Verilog?

• assign

• always

• initial

• wire

Dataflow modeling is most suitable for describing:

• Sequential circuits

• Simple combinational circuits

• Complex sequential circuits

• Memory blocks

In dataflow modeling, which data type is typically used for signals?

• reg

• wire

• integer

• real

The continuous assignment statement 'assign y = a & b;' is an example of which modeling style?

• Structural

• Dataflow

• Behavioral

• Mixed

In dataflow modeling, the 'assign' statement continuously drives the value to a wire.

• True

• False