Computer Architecture Quiz

In the following memories read and write operations will be will be completed in the same amount of time.

• RAM

• ROM

• EPROM

• BIOS

SRAM and DRAM chips are -----------

• Volatile

• Non-Volatile

• Only Read

• Non-erasable

MAR stands for ___________

• Memory address register

• Main access register

• Main addressable register

• Memory accessible register

A RAM IC is specified by 8K X 16. The number of address lines required to access all the 8K locations present in the chip are?

• 18

• 16

• 13

• 12

In certain applications, there is a requirement of 16K X 8 memory. But 8K X 4 chips are available. How many chips are required?

• 4

• 2

• 8

• 6

RAID stands for

• Random access Iron disk

• Redundant array of Independent disks

• Read and independent disk

• Read and Input disk

RAID1 differs from RAID 2 through 6 in achieving the redundancy

• RAID 1 uses parity

• RAID 2 to 6 uses parity

• RAID uses simple duplicate

• RAID uses stripping

A magnetic disk has a magnetic coating on both sides, with 5 tracks and 10 sectors. Each sector has 10KB of data. The capacity of the disk is

• 2.5 MB

• 25 MB

• 25 KB

• 2.5 KB

Cache memory contains three levels namely L1, L2, and L3 respectively. The speed performance of L1- L3 are as follows

• L1>L2

• L1

• L1l3

• L1>L2>L3

The nature of the cache is

• DRAM

• SRAM

• ROM

• Flash