QUIZ-1

Which among the following is a process of transforming RTL to a gate-level netlist?

• Simulation

• Optimization

• Synthesis

• Verification

The output of the following logic =?

• logic 0

• logic 1

• x

• z

#40 $finish indicates

• End of simulation time

• End of simulation at 40-time units

• Suspend simulation at 40-time units

•  

  None

The output of the following logic =?

• Logic 0

• Logic 1

• X

•  

  Z

Which model uses transistors as their basic components?

• Switch level

• Gate Level

• Behavioral

• Layout Level

What is the default value of the reg data type?

• 0

• 1

• x

• z

What is the time period of clock #20 clock = ~clock?

• 10

• 20

• 40

• 80

A 2-input XOR gate can be worked as an Inverter (NOT Gate) if a =? & b =?

• A = a  , b =0

• A = a  , b =1

• A = b  , b= a

• None

•  P – 3   Q – 2  R – 1

•  P – 3   Q–1   R – 2

• P – 2    Q –3    R –1

•  

  None

VHDL stands for

• Very High-Speed Integrated Circuit Hardware Description Language

• Very High Description Langauge

• Verilog Hardware Description Language

• None