DSD ACTIVITY BASED LEARNING QUIZ

The invalid range for an input to TTL logic is from ________.

• 0 to 0.8 V

• 1.2 to 1.6 V

• 0.8 to 2.0 V

• 2.0 to 5.0 V

The combination of waveforms consisting of the given figures 1 and 2 is generally referred to as ________.

• simultaneous waveforms

• a timing diagram

• two-phase waveforms

• pulse waveforms

The given figure is most likely a ________.

• register

• decoder

• counter

• multiplexer

If a HIGH logic level is assigned a binary zero (0), and a low level is assigned a binary one (1), the logic is called ________.

• negative logic

• positive logic

• invalid logic

• assertion-level logic

How many flip flops are needed to design MOD 4 counter?

• 2

• 3

• 4

• 5

In Johnson counter, Q_A,Q_B,Q_C,Q_D values are 1000 respectively. When clock pulse is given to the counter,what will be the output of each flipflop?

• 1100

• 0100

• 1111

• 1001

Identify the type of hazard present in the digital circuit.

• Static 1

• Static 0

• Dynamic

• Functional

Identify the type of hazard present in the digital circuit.

• Static 1

• Static 0

• Dyanamic

• Functional

How many AND and OR gates are required to implement the following boolean function using PAL?

f1=A(B+C)

f2=A

• 2,2

• 3,2

• 4,2

• 2,1

To implement half adder using PAL, how many AND and OR gates are needed?

• 3,2

• 2,2

• 2,1

• 1,1