Verilog HDL Quiz

Which of the following is a correct file extension for Verilog files?

• .vhdl

• .verilog

• .vlg

• .v

Verilog HDL is mainly used for:

• High-level programming

• Hardware description

• Web development

• Game design

Which of the following is not a modeling style in Verilog?

• Behavioral

• Structural

• Object-Oriented

• Dataflow

In Verilog, the module keyword is used to:

• End a simulation

• Declare a block of code

• Define a hardware component

• Allocate memory

Which symbol is used to denote a comment in Verilog (single-line)?

• #

• //

• **

• /* */

Which keyword is used to end a Verilog module?

• done

• finish

• endmodule

• complete

Which of the following is a Verilog gate primitive?

• if

• and

• loop

• wait

The sensitivity list of an always block is enclosed in:

• []

• {}

• ()

• <>

Which of the following is a valid Verilog data type?

• bitset

• bit

• wire

• binary

The default time unit used in Verilog simulation is:

• Seconds

• Milliseconds

• Nanoseconds

• Femtoseconds