
Pseudo NMOS Logic Quiz

Quiz
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Other
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University
•
Hard
penumalli koteswararao
FREE Resource
11 questions
Show all answers
1.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In a Pseudo-NMOS inverter, the pull-up transistor is:
An enhancement-mode PMOS
A depletion-mode NMOS
A resistor
A clocked NMOS
2.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
In a Pseudo-NMOS inverter, the PMOS transistor is:
Connected to the clock
Permanently ON
Controlled by input logic
Connected in series with NMOS
3.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
What happens to the output high voltage (VOHV_{OH}VOH) in a pseudo-NMOS inverter when the NMOS is OFF?
It is zero
It is undefined
It rises to VDDV_{DD}VDD
It is equal to the threshold voltage
4.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which factor significantly affects the output high voltage (VOHV_{OH}VOH) in a pseudo-NMOS inverter?
PMOS gate width
NMOS gate capacitance
Strength ratio of PMOS and NMOS
Fan-out load only
5.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
The threshold voltage (VthV_{th}Vth) of the inverter is typically:
At VDD/2V_{DD}/2VDD/2
Higher than VDDV_{DD}VDD
Defined by NMOS alone
Shifted due to always-on PMOS
6.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Compared to CMOS inverter, the pseudo-NMOS inverter consumes:
Less power
No static power
More static power
Equal power
7.
MULTIPLE CHOICE QUESTION
30 sec • 1 pt
Which of the following best describes the operation of the pseudo-NMOS inverter at logic '0' input?
Both NMOS and PMOS are OFF
NMOS is ON, PMOS is OFF
NMOS is OFF, PMOS is ON
Both NMOS and PMOS are ON
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