Instruction Set Architecture (ISA) quiz

What best describes the role of an Instruction Set Architecture (ISA)?

• It controls network communication protocols

• It determines the screen resolution of a computer

• It serves as an interface between hardware and software

• It defines the structure of an operating system

Which of the following is not a typical component of an ISA?

• Instruction Set

• Data Types

• Disk Storage Format

• Addressing Modes

Where does the ISA lie in the system architecture?

• Between the user interface and applications

• Between the hardware and machine-level software

• Between RAM and cache memory

• Between CPU and I/O devices

What is a defining characteristic of CISC architecture?

• Only one instruction format

• Uses fixed-length instructions

• Includes many addressing modes and complex instructions

• Prioritizes low-level code efficiency over code density

What is a key advantage of RISC architecture?

• Requires more transistors and logic gates

• Uses variable-length instructions

• Optimized for pipelining and faster execution

• Minimizes instruction count by increasing complexity

Which of the following correctly compares CISC and RISC architectures?

• RISC has more addressing modes than CISC

• CISC uses fixed-length instructions, RISC uses variable-length

• RISC typically completes one instruction per clock cycle

• CISC is better suited for pipelining

Which equation best represents execution time in a CPU?

• Clock Rate ÷ CPI

• (Instruction Count) × (CPI) × (Clock Cycle Time)

• Memory Size × Clock Rate

• (Instruction Length) + (Clock Speed)

Why is RISC architecture better suited for pipelining?

• It uses microprogramming

• It includes complex instructions

• It has simpler and fixed-length instructions

• It consumes more power

How does ISA affect compiler efficiency?

• CISC architectures reduce compiler optimization needs

• RISC instructions are optimized for hardware complexity

• RISC compilers are less efficient due to low-level control

• CISC increases the need for advanced compiler design

What is a consequence of the hardware complexity in CISC CPUs?

• Increased battery life

• Simplified instruction decoding

• Difficulty in optimizing for performance

• Smaller chip size