Flip Flop Quiz

The truth table for an S-R flip-flop has how many VALID entries?

• 1

• 2

• 3

• 4

In S-R flip-flop, if Q = 0 the output is said to be ___________

• Set

• Reset

• Previous state

• Current state

The flip-flops which has not any invalid states are _____________

• S-R, J-K, D

• J-K, D, T

• J-K, D, S-R

• S-R, J-K, T

What does the circle on the clock input of a J-K flip-flop mean?

• Level enabled

• Positive edge triggered

• negative edge triggered

• Level triggered

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________

• The clock pulse transitions from HIGH to LOW

• The clock pulse is HIGH

• The clock pulse is LOW

• The clock pulse transitions from LOW to HIGH

Sequential circuit contains

• Atleast one memory element

• No memory element

• None of the above

• All inputs applied simultaneously

T Flip flop is used as

• Toggle switch

• Transfer data circuit

• Time delay switch

• None of the above

A counter circuit is usually constructed of ____________

• A number of latches connected in cascade form

• A number of NAND gates connected in cascade form

• A number of flip-flops connected in cascaded

• A number of NOR gates connected in cascade form

The advantage of a J-K flip-flop over an S-R FF is that ________.

• it has no invalid states

• it has fewer gates

• it has only one output

• it does not require a clock input

Following flip flop is used to eliminate race around problem

• Master Slave Flip flop

• D Flip flop

• SR Flip flop

• JK Flip flop