System Verilog

Identify the person who developed Verilog in the 1980s?

• Phil Moorby and Cadence Design Systems

• Dennis Ritchie and Brian Kernighan

• James Gosling and Sun Microsystems

• John Backus and IBM

Identify the abstraction levels supported by Verilog for describing hardware

• Behavioral, RTL, and gate-level

• High-level synthesis only

• Assembly and machine code

• Only gate-level descriptions

Interpret the relationship between testbench and a Verilog module.

• It simulates input data and monitors the outputs.

• It directly synthesizes the hardware into an FPGA.

• It is used to write the HDL code for the design.

• It performs real-time signal processing.

Discriminate the effect of using <= (non-blocking assignment) in Verilog.

• It schedules the variable update to occur after the current time step.

• It updates the variable immediately after the statement is executed.

• It is used for initializing variables only.

• It restricts the variable from being updated.

Compare the primary difference between wire and reg in Verilog.

• A wire represents physical connections, while a reg stores values for procedural assignments.

• A wire stores values, while a reg carries signals.

• A reg cannot be assigned values, while a wire can.

• A wire is used for procedural assignments, while a reg is used for continuous assignments.

Examine how the assign and always blocks in a Verilog module impacts simulation.

• The assign block and always block run independently unless explicitly combined.

• The assign block will override any logic in the always block.

• The always block will take precedence over the assign block.

• The module will cause a simulation error due to conflicting assignments.

Evaluate the use of = assignment operator in Verilog, which type of assignment is performed.

• Blocking assignment

• Procedural assignment

• Continuous assignment

• Non-blocking assignment

Analyse the events that occur when a wire is allocated to more than one driver in Verilog.

• It causes a race condition, and the wire's value is undefined.

• The simulator will select one of the drivers randomly.

• The final value of the wire will be determined by the first driver.

• It will cause a synthesis error.

Select the distinction between Verilog's case statement and if-else statement

• case is typically used with a single variable, whereas if-else can handle complex conditions.

• There is no difference; both are used interchangeably.

• case executes statements in parallel, while if-else executes them sequentially.

• case is used for simple conditional checks, while if-else allows for multiple conditions

Estimate the declaration of a 4-bit input vector in Verilog.

• input [3:0] a;

• input a[4];

• input a : 4;

• input [4] a;