2110 FINAL REVIEW!!!!

2110 FINAL REVIEW!!!!

University

17 Qs

quiz-placeholder

Similar activities

Data Structure

Data Structure

University

15 Qs

AVL Trees

AVL Trees

KG - University

12 Qs

Data Structure Quiz1

Data Structure Quiz1

University

20 Qs

Computer Network Chapter 1 part 1

Computer Network Chapter 1 part 1

University

15 Qs

Computer Specification Literacy

Computer Specification Literacy

University

20 Qs

Motherboards

Motherboards

University

20 Qs

KAMALUDDEEN IBRAHIM YARIMA

KAMALUDDEEN IBRAHIM YARIMA

University

20 Qs

Skip List Quizizz

Skip List Quizizz

9th Grade - University

12 Qs

2110 FINAL REVIEW!!!!

2110 FINAL REVIEW!!!!

Assessment

Quiz

Computers

University

Medium

Created by

Annelise Lloyd

Used 183+ times

FREE Resource

17 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Convert the following decimal number to hexadecimal (unsigned): 250

xFA

x7D

xEA

x7B

2.

MULTIPLE SELECT QUESTION

1 min • 1 pt

Which of the following additions of a pair of 4-bit two’s complement numbers causes overflow (select all that apply)?

1010 + 1011

0010 + 1001

1110 + 1100

0111 + 0100

3.

MULTIPLE CHOICE QUESTION

45 sec • 1 pt

Media Image

What gate is this? If we add an inverter, then what gate would we have?

NAND, OR

NAND, AND

NOR, OR

NOR, AND

4.

MULTIPLE CHOICE QUESTION

1 min • 1 pt

Media Image

What does the circuit do?

Negates A if B==7, negates B if B==0, outputs 0 otherwise

Negates B if B==7, negates A if B==0, outputs 0 otherwise

Negates A if B==7, outputs 0 if B==0, negates B otherwise

Negates B if B==7, outputs 0 if B==0, negates A otherwise

5.

MULTIPLE CHOICE QUESTION

1 min • 1 pt

Which of the following K-Maps has correct groupings? (Yellow-green and yellow-orange are overlaps.)

Media Image
Media Image
Media Image
Media Image

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Typically, a register is an example of _______ logic and is made up of _______.

Sequential, D Flip Flop

Sequential, Gated D latch 

Combinational, D Flip Flop

Combinational, Gated D latch 

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In a D flip-flop, what happens when the clock edge jumps from 0 to 1 and the input is high?

The output becomes low

The output remains unchanged

The output follows the input

Depends on the location of the not gate

Create a free account and access millions of resources

Create resources
Host any resource
Get auto-graded reports
or continue with
Microsoft
Apple
Others
By signing up, you agree to our Terms of Service & Privacy Policy
Already have an account?