DSD QUIZZ 2 2023 Batch

DSD QUIZZ 2 2023 Batch

10 Qs

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DSD QUIZZ 2 2023 Batch

DSD QUIZZ 2 2023 Batch

Assessment

Quiz

others

Easy

Created by

Radhika Senthil

Used 3+ times

FREE Resource

10 questions

Show all answers

1.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which model uses transistors as their basic components
Switch level
Gate Level
Circuit Level
Layout Level

2.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

State true or false for the statement ‘Verilog is case sensitive’
True
False

3.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is Verilog?
A programming language for hardware description
A high-level programming language for software development
A data visualization tool
An operating system

4.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

Which one of the following represents a hardware component in Verilog
Module
Function
Loop
Variable

5.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the purpose of ‘assign’ statement in Verilog
To initialize variables
To specify input/output ports of a module
To implement continuous assignments for combinational logic
To define a new module

6.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

In RTL Design, What is a ‘register’
A clock signal generator
A storage element for data
An arithmetic logic unit (ALU)
A type of programming language

7.

MULTIPLE CHOICE QUESTION

30 sec • 1 pt

What is the default value of the reg data type
0
1
Z
X

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