Chapter 15: RISC CISC and Pipelining

What is the primary purpose of pipelining in CPU architecture?

• To increase memory capacity

• To allow multiple instructions to be processed simultaneously

• To reduce power consumption

• To increase the size of the instruction set

In the context of pipelining, what does the term "pipeline stall" refer to?

• When the CPU overheats

• When an instruction fails to decode

• When the next instruction cannot execute in the next clock cycle

• When the power supply is interrupted

Which stage of the Fetch-Execute Cycle is responsible for retrieving an instruction from memory?

• Decode

• Execute

• Write Back

• Fetch

Which of the following is a key characteristic of RISC architecture?

• Complex instruction sets

• Variable instruction length

• Single-cycle instruction execution

• Extensive use of microcode

In a pipelined CPU, what happens during the "Decode" stage?

• The CPU retrieves the instruction from memory

• The CPU decodes the instruction to understand what needs to be done

• The CPU executes the instruction

• The CPU writes the result to memory or a register

What is the main advantage of using CISC (Complex Instruction Set Computer) architecture?

• Faster execution of simple tasks

• Reduced need for complex software

• Simpler hardware design

• Fewer instructions per program

In a pipelined CPU, which instruction stage follows the "Execute" stage?

• Fetch

• Decode

• Write Back

• Operand Fetch

Which of the following best describes an interrupt in the context of CPU operations?

• A signal that temporarily halts the CPU

• A process that speeds up instruction execution

• A method to increase the clock speed

• A way to enhance memory performance

How does pipelining improve the overall performance of a CPU?

• By increasing clock speed

• By reducing the instruction set size

• By processing multiple instructions at different stages simultaneously

• By simplifying the decode stage

What is a potential drawback of pipelining in CPU architecture?

• Increased instruction set size

• Complexity in handling interrupts

• Lower overall performance

• Reduced memory capacity