pahc 7

The Intel 80186/80286 microprocessor has the following architecture:

• [<$>] 4-bit

• [<$>] 32-bit

• [<$>] 16-bit

• [<$>] 8- bit

Which of the following computer lines is capable of processing floating point:

• [<$>] 80386

• [<$>] 80286

• [<$>] 80186

• [<$>] 80486

At the microarchitecture level, the PUSH instruction performs operations (note: ac (accumulator); sp (stack pointer); m (memory))

• [<$>] sp:=sp-1; m[sp]:=ac

• [<$>] m[ac]:=m[sp]; sp:=sp+1

• [<$>] sp:=sp-1; m[sp]:=m[ac]

• [<$>] ac:=m[sp]; sp:=sp+1

The Intel 8008/8080 microprocessor has the following architecture:

• [<$>] 4-bit

• [<$>] 8-bit

• [<$>] 16-bit

• [<$>] 32-bit

At the microarchitecture level, the LODL instruction performs operations (note: ac (accumulator); sp (stack pointer); m (memory); x (address value))

• [<$>] ac:=m[sp+x]

• [<$>] ac:=m[x]

• [<$>] m[x]:=ac

• [<$>] m[sp+x]:=ac

At the microarchitecture level, JPOS instructions perform operations (note: ac (accumulator); pc (program counter); x (address value))

• [<$>] if ac=0 then pc:=x

• [<$>] if ac <> 0 then pc:=x

• [<$>] if ac < 0 then pc:=x

• [<$>] if ac ≥ 0 then pc:=x

At the microarchitecture level, the SUBD instruction performs operations (note: ac (accumulator); sp (stack pointer); m (memory); x (address value))

• [<$>] ac:=ac+m[sp+x]

• [<$>] ac:=ac-m[sp+x]

• [<$>] ac:=ac-m[x]

• [<$>] ac:=ac+m[x]

At the microarchitecture level, the JNZE instruction performs operations (note: ac (accumulator); pc (program counter); x (address value))

• [<$>] if ac ≥ 0 then pc:=x

• [<$>] if ac < 0 then pc:=x

• [<$>] if ac=0 then pc:=x

• [<$>] if ac <> 0 then pc:=x

The Intel Celeron processor has an architecture of

• [<$>] 64-bit

• [<$>] 8-bit

• [<$>] 16-bit

• [<$>] 32-bit

The Intel 80386/80486 microprocessor has the following architecture:

• [<$>] 8-bit

• [<$>] 16-bit

• [<$>] 32-bit

• [<$>] 64-bit