COA_Ch06_InClass-3

If a cache access requires one clock cycle and dealing with cache misses requires an additional five clock cycles, which of the following cache hit rates results in an effective access time of 2 clock cycles?

• 70%
• 80%
• 85%
• 90%
• 95%

A unified cache is a cache that holds both data and instructions.

• True
• False

Cache memory improves performance by improving memory __________ while virtual memory improves performance by increasing memory _____________.

• execution time/access time
• locality/access time
• access time/address space
• organization/paging

When a computer uses paging, there must be a page table for every process.

• True

• False

The purpose of a TLB is:

• to cache page table entries
• to cache frequently used data from memory
• to hold the starting address of the page table
• to hold the length of the page table