Digital Application

Unused inputs of the CMOS chip have to be connected to

• a buffer

• a pull-up resistor

• ground

• a resistor

• supply

CMOS logic family dominates the Large Scale Integrated (LSI) chip as compare to TTL logic family is/are

• consume less power

• wider range of supply voltage

• operate at faster sample in low supply voltage

• better tolerance to noise

• better tolerance to ESD

The following is true for using 'conductive foam' when shipping CMOS devices

• To ensure electrostatic charge build up between all terminals

• To allow user to touch the terminals easily

• To keep all the terminals at the different potential so that electrostatic charge build up can be prevented

• To keep all the terminals at the same potential so that electrostatic charge build up can be prevented

All used inputs of CMOS chips need to be connected to

• prevent incorrect operation due to noise pickup

• allow excessive power dissipation

• allow overheating of CMOS chip

• ensure all pins are connected in a systematic method

Refer to the truth table. Which of the following expressions is the SOP Boolean expression?

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The Looping Group of 4 (Quads) will eliminate

• 1 variable

• 2 variables

• 3 variables

• 4 variables

• 0 variable

The Looping Group of Octets of 1 will eliminate

• 1 variable

• 2 variables

• 3 variables

• 4 variables

• 8 variables

The output of a 3-input NOR gate is high when

• all inputs are high

• all inputs are low

• one of the inputs is low

• one of the inputs is high

• all inputs are connected together and set to high

The simplified expression using the Karnaugh Map is

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The general troubleshooting guidelines are:

• 1. Step 1. Fault detection

  2. Step 2. Fault isolation

     Step 3. Fault correction

• 1. Step 1. Fault isolation

  2. Step 2. Fault detection

  3. Step 3. Fault correction

• Step 1. Fault correction

  Step 2. Fault isolation

  Step 3. Fault detection

• Step 1. Fault correction

  Step 2. Fault detection

  Step 3. Fault isolation