STA -1

In below options, how many values can be used for representing Analog signal?

• 2

• 4

• Infinite

• 8

In _____ family it is possible to integrate the multifunction blocks together.

• SSI

• VLSI

• MSI

• LSI

At which phase of VLSI flow the RTL code is converted in to gate level netlist:

• RTL simulation

• Synthesis

• Timing verification

• Formal verification

Which is the fastest method of timing verfication

• RTL level simulation

• Dynamic timing analysis

• Static timing analysis

• formal verification

Which latch dissipates more power:

• Static Latch

• None of the above

• Dynamic Latch

• Both (a) and (b)

What is required for Floorplan, Placement and Routing of the design? Tick which is correct opton?

• RTL code

• Netlist

• Parasitics

• None of these

Which is correct option for rise time?

• Signal Value from 10% to 90%

• Signal Value from 90% to 10%

• Singnal Value is constant

• None of the above

Cell and Net delay value calculated by ____. Tick the correct option

• Resistance (R) Value

• Capacitance (C) value

• Resistance (R) and Capacitance (C) value

• None of the above

_____ is the cause for delay.

• Temperature

• Transition

• Fanout

• All of the above

Critical path is calculated based on_____

• Number of gates in a path

• Number of flip-flops in a path

• Amount of total delay in a path

• Long wired path