1.1.2 Types of Processor

Which processor design does the following statement relate to, 'more RAM is needed to store the instructions'?

• RISC

• Both

• CISC

• Neither

Which of these statements is true?

• It is not possible to say one architecture is faster than the other, there are too many other factors to consider

• RISC is faster than CISC

• CISC is faster than RISC

• RISC and CISC will always operate at the same speed because program code is always compiled to the same single machine code

Which processor design does the following statement relate to, 'uses a load-store approach where the operands for an add operation must both be held in registers'?

• RISC

• Both

• Neither

• CISC

Which of the following is NOT a reason why doubling the number of processor cores does not lead to a direct doubling of processor speed and efficiency in all situations?

• Multi-core processors are rarely used

• Many problems are not fully parallelisable

• Writing programs to take advantage of multiple cores can be complex

• There are overheads in terms of communication between multiple cores

What does 'CISC' stand for?

• Complex Instruction Set Computer

• Complete Instruction Set Controller

• Complex Instruction Set Controller

• Complete Instruction Set Computer

Which processor design does the following statement relate to, 'instruction is executed in one clock cycle'?

• RISC

• Both

• CISC

• Neither

Which of the following is the best definition for 'SIMD'?

• A single operation carried out on many pieces of data at the same time

• Different instructions carried out at the same time on different pieces of data

• A single operation carried out on a single piece of data at a time

• Different operations carried out on the same piece of data at the same time

Which processor design does the following statement relate to: 'a limited number of addressing modes'?

• RISC

• Neither

• CISC

• Both

Which processor design does the following statement relate to, 'uses a register-memory approach where the operands for an add operation can be held one in memory and one in a register'?

• CISC

• RISC

• Both

• Neither

Which processor design does the following statement relate to, 'pipelining is possible - that is fetching the next instruction whilst decoding current instruction'?

• RISC

• Neither

• CISC

• Both