last week

What are the deliverables of FCFP to tile? Select all that applies. (Select more than 1 answers)

• SDC

• Def

• Ports location

• Standard cells location

What are the things FCFP take care of?

• Fullchip DRC

• Fullchip timing

• Fullchip pin placement

• None of the above

In what circumstances do a tile owner need to feedback to FCFP owner?

• Getting unreasonable tile utilization at floorplan stage

• Seeing timing violation due to physical distance of ports

• Two ports are placed at the same location and same metal layer causing short

• All of the above

At which of the following utilization of TileA should tile owner raise a concern to FCFP?

• 10%

• 60%

What is the different between pnr & eco?

• Both pnr and eco can build clock

• Pnr and eco can edit floorplan

• Eco can take in tune respin from synthesis; pnr cannot

• Both pnr and eco flow can move register

In MTO, what can you do for functional ECO? (Select more than 1 answers)

• Reroute on metal layer

• Use spare cell to connect logic

• add buffer to fix hold

• Bounding to fix setup

• Push/Pull clock for timing violations

What is "Id" here represent?

• Sub-threshold current

• Gate induced leakage

• Gate oxide leakage

• Diode reverse bias current

Which statements is true for ISOLATION CELL?

• It is required for signal propagate from ON power domain to OFF power domain

• It is required for signal propagate from OFF power domain to ON power domain

• all are true

Which are the cells used in low power cells techniques coded in UPF file? (Select more than 1 answers)

• Isolation cell

• Level shifter cell

• Clock gating cell

• power switch cell

Why low power has become an important issue in the present day VLSI circuit realization?

• Increasing transistor count

• Higher speed/performance of operation

• Greater device leakage currents

• all of above