DSD using Verilog

femto second means ------------

• 10 power -12

• 10 power -16

• 10 power -15

• 10 power -09

Odd parity code for data 1110 is -----------------

• 0

• x

• z

• 1

If in1 = 4’b101x and in2 = 4’b0101 then in1 + in2 equals

• None

• x

• 0110

• 0111

Verilog is case sensitive.

• False

• True

Which is legal negative number

• 4'd-3

• -6d'3

• 6'-d3

• None of the given options

-10 % 3 evaluates to

• -1

• 1

• x

• 0

Universal gates set are :

• OR, AND

• EXOR, EXNOR

• NAND, NOR

• None of the given options