RTL DESIGN

wire can be driven by multiple drivers.

• True

• false

What are the possible values of == operator

• 0,1

• 0,x

• 1,x

• 0,1,x

-10 % 3 evaluates to

• -1

• 1

• 0

• X

If in1 = 4�b101x and in2 = 4�b0101 then in1 + in2 equals

• 0111

• 0110

• x

• None of these

In continuous assignment left hand side must be

• Net

• Reg

• Scalar or Vector Net

• Scalar or Vector reg

Parameter value can be overridden at module instance by

• Specparam

• Defparam

• Parameter

• None

Turn off delay means, gate output transition to

• 1

• 0

• z

• x

What is system task to suspend simulation

• $finish

• $minitor

• $display

• $stop