Higher CS - Computer Structure flascards

Front

Fetch/Execute Cycle

Back

Process of sending and receiving data to/from processor and memory

Front

Components in use during Fetch/Execute Cycle

Back

Control Unit, Data Bus, Address Bus, memory Address Register, Memory Instruction Register

Front

Role of Control Unit in Fetch/Execute Cycle

Back

Dictates clock speed and activates read/write line

Front

MDR (Memory Data Register)

Back

Passes data to be written to the data bus

Front

Fetch Execute Cycle - Step 1

Back

Address bus setup by processor with address to be read from

Front

Fetch Execute Cycle - Step 2

Back

Read line activated on control bus

Front

Fetch Execute Cycle - Step 3

Back

Instruction transferred along the data bus to the processor

Front

Fetch Execute Cycle - Step 4

Back

Instruction interpreted and executed

Front

Processor components

Back

Control unit, arithmetic and logic unit (ALU), registers

Front

Cache memory location

Back

Located on or next to a processor